The present invention relates to a semiconductor device and a manufacturing method thereof, and, more particularly, to a method of forming line patterns having high aspect ratios indispensable to manufacture of a NAND-flash memory having a three-dimensional structure.
With demands for semiconductor devices with higher speed and higher density, semiconductor devices having three-dimensional structures are being developed actively in recent years. For example, “Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory” by J. Jang, et al., Proceedings of 2009 Symposium on VLSI Technology, pp. 192-193 discloses an example of a 3D NAND-flash memory (hereinafter, abbreviated as 3D-NAND). FIGS. 1A to 1C schematically show three orthogonal views of a 3D-NAND memory cell. FIG. 1A shows a top view of the 3D-NAND memory cell viewed from above, FIG. 1B shows a side view of the top view of FIG. 1A viewed from the right side of the sheet (the structure viewed in the y direction), and FIG. 1C shows a front view of the top view of FIG. 1A viewed from the bottom side of the sheet (the structure viewed in the x direction). The memory cell actually extends long in the lateral direction (in the y direction) of the sheet, and each of FIG. 1A and FIG. 1C shows only ends of the both sides of the memory cell. In FIG. 1A, incidentally, bit lines 33 and word lines 34 shown in FIG. 1C are omitted from showing in the drawing.
The above 3D-NAND memory cell has a structure that control gate layers 30, each of which comprises a multi-layered film of a tungsten film 5 (a conductive film) and a SiO2 film 3 (an insulating film), are additionally stacked stepwise on a semiconductor substrate (a Si substrate) 1 and cylindrical channel holes 4 which are filled with polysilicon are formed therein, as shown in FIG. 1C. Incidentally, in the initial stage of the manufacturing process, the control gate layer 30 is formed as a multi-layered film of a Si3N4 film and a SiO2 film 3, and the Si3N4 film is replaced by the tungsten film 5 during the manufacturing process. To operate the tungsten film 5 included in the control gate layer 30 as the gate electrode, the control gate layers 30 are stacked stepwise to form a terrace structure and are respectively connected with the word lines 34 through contact holes 35. The multi-layered films of the control gate layers 30 are called hereinafter as a control gate group 31 for convenience. The control gate group 31 is divided in the x direction by trenches (spaces) 32 as shown in FIG. 1B and has a line-and-space structure as shown in FIG. 1A when viewed from above.
A contact hole 6 is formed on the channel hole 4 and connected to the bit line 33 further formed on it. An ONO film, which is not shown in the drawing, is formed as a charge trap material on the inner wall surface (an interface between wall surfaces of holes formed in the control gate groups 31 and pillars of polysilicon filled therein) of the channel hole 4 and operates as a capacitor of the memory cell.
The 3D-NAND memory cell disclosed in “Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory” by J. Jang, et al., Proceedings of 2009 Symposium on VLSI Technology, pp. 192-193 has a characteristics that the control gate group 31 is divided in the x direction by the trenches 32 as shown in FIG. 1B. These trenches 32 are formed by etching. FIG. 2 shows in Part (A) and Part (B) patterns before and after the process of forming the trenches 32 in the same side views as FIG. 1B. Part (A) of FIG. 2 shows the pattern before etching, and Part (B) of FIG. 2 shows the pattern after etching, respectively. In the state before etching shown in Part (A) of FIG. 2, the control gate layers 30 each of which comprises the above-described multi-layered film of the Si3N4 film 2 and the SiO2 film 3 are stacked on the Si substrate 1, and the channel holes 4 which are filled with polysilicon are formed therein. A line-and-space resist pattern is formed on its top surface by lithography, and the trenches 32 shown in Part (B) of FIG. 2 are formed by dry etching with it as a mask.
In the memory cell shown in FIGS. 1A to 1C, the control gate group has eight of the control gate layers 30 stacked together; for a higher density, however, it is necessary to increase the number of the stacked layers or to reduce the interval of channel holes in the x and y directions by reducing the diameters of the channel holes 4. For example, “Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory” by J. Jang, et al., Proceedings of 2009 Symposium on VLSI Technology, pp. 192-193 proposes as future developments that cost per bit (bit cost) is reduced by setting the number of the stacked layers of the control gate layers 30 to 128 layers and/or reducing the diameters of the channel holes 4 to 45 nm.